Daniel Lustig


Research Scientist
NVIDIA Corporation
Santa Clara, CA 95050

Email: dlustig at nvidia dot com

[CV] [Google Scholar]

Recent Awards

COATCheck chosen as one of the IEEE Micro Top Picks of 2016!

CCICheck nominated for Best Paper at Micro 2015!

PipeCheck chosen as one of the IEEE Micro Top Picks of 2014!

PipeCheck nominated for Best Paper at Micro 2014!

Intel PhD Fellowship, 2014

Education

Ph.D., Princeton University, November 2015
Advisor: Margaret Martonosi
Dissertation Title: "Specifying, Verifying, and Translating Between Memory Consistency Models"
[PDF]

M.A., Princeton University, September 2011

B.S.E., University of Pennsylvania, May 2009

Publications

"Transistency Models: Memory Ordering at the Hardware-OS Interface",
Daniel Lustig, Geet Sethi, Abhishek Bhattacharjee, and Margaret Martonosi
IEEE Micro, 37 (3) (Top Picks of 2016), May-June 2017

"Automatic Synthesis of Comprehensive Memory Model Litmus Test Suites",
Daniel Lustig, Andrew Wright, Alexandros Papakonstantinou, and Olivier Giroux
22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xi'an, China, April 2017
[PDF] [Slides] [Website]

"TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA",
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, and Margaret Martonosi
22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xi'an, China, April 2017
[PDF] [Slides] [Website]

"COATCheck: Verifying Memory Ordering at the Hardware-OS Interface",
Daniel Lustig*, Geet Sethi*, Margaret Martonosi, and Abhishek Bhattacharjee,
21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Atlanta, GA, April 2016
(*: joint first authors)
[PDF] [Slides] [Website][Online Tool]

"CCICheck: Using μhb Graphs to Verify the Coherence-Consistency Interface",
Yatin Manerkar, Daniel Lustig, Michael Pellauer, and Margaret Martonosi,
48th International Symposium on Microarchitecture (MICRO), Waikiki, HI, December 2015
Nominated for Best Paper!
[PDF] [Slides] [Website]

"Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures"
Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy Allmon, Neal Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel Emer
ACM Transactions on Computer Systems (TOCS), 33(3), September 2015

"ArMOR: Defending Against Consistency Model Mismatches in Heterogeneous Architectures",
Daniel Lustig, Caroline Trippel, Michael Pellauer, and Margaret Martonosi,
42nd International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015
[PDF] [Extended PDF] [Slides] [Website]

"Verifying Correct Microarchitectural Enforcement of Memory Consistency Models",
Daniel Lustig, Michael Pellauer, and Margaret Martonosi,
IEEE Micro, 35 (3) (Top Picks of 2014), May-June 2015

"PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models",
Daniel Lustig, Michael Pellauer, and Margaret Martonosi,
47th International Symposium on Microarchitecture (MICRO), Cambridge, UK, December 2014
Nominated for Best Paper!
Chosen by IEEE Micro Top Picks as one of the best computer architecture papers of 2014!
[PDF] [Slides] [Website]

"Efficient Spatial Processing Element Control via Triggered Instructions",
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy Allmon, Rachid Rayess, Stephen Maresh, and Joel Emer,
IEEE MICRO, 34 (3) (Top Picks of 2013), May-June 2014

"Triggered Instructions: A Control Paradigm for Spatially-Programmed Architectures",
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy Allmon, Rachid Rayess, Stephen Maresh, and Joel Emer,
40th International Symposium on Computer Architecture (ISCA), Tel Aviv, Israel, June 2013
[PDF]

"TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs",
Daniel Lustig, Abhishek Bhattacharjee, and Margaret Martonosi,
ACM Transactions on Architecture and Code Optimization (TACO), 10 (1), April 2013

"Reducing GPU Offload Latency via Fine-Grained CPU-GPU Synchronization",
Daniel Lustig and Margaret Martonosi,
19th International Symposium on High Performance Computer Architecture (HPCA), Shenzhen, China, February 2013
[PDF]

"Shared Last-Level TLBs for Chip Multiprocessors",
Abhishek Bhattacharjee, Daniel Lustig, and Margaret Martonosi,
17th International Symposium on High Performance Computer Architecture (HPCA), San Antonio, TX, February 2011
[PDF]

"The Algebraic Independence of the Sum of Divisors Functions",
Daniel Lustig,
Journal of Number Theory, 130 (11), November 2010.
[PDF]